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digital signal processor for cdp s5l986f01 1 digital signal processor the s5l9826f01 is a cmos integrated circuit designed for the digital audio signal processor for compact disc player. it is a monolithic ic that builts-in 16-bit digital analog convertor, esp interface and digital de- emphasis additional conventional dsp function. features ? efm data demodulation ? frame sync detection / protection / insertion ? powerful error correction (c1: 2 error; c2: 4 erasure) ? interpolation ? 8fs digital filter (51th+13th+9th) ? subcode data serial output ? clv servo controller ? micom interface ? digital audio output ? digital de-emphasis ? esp interface ? built-in 16k sram ? built-in digital pll ? double speed play available ? built-in 16-bit d/a converter ?v dd = 5v ordering information device package tempe. range S5L9286F01-q0r0 80-qfp-1420c -20 o c ? +75 o c 80-qfp-1420c
S5L9286F01 digital signal processor for cdp 2 block diagram cntvol 66 efmi 5 3 dpfin 4 2 dpfout dpdo 72 73 75 76 70 smef smon smdp smds lock 9 8 xout xin 37 38 36 69 68 mdat mck mlt trcnt /istat 61 62 63 65 xtalsel fok cdrom test1 7 datx 19 20 rchout lchout 22 vrefh1 17 vrefl1 24 80 67 77 14 12 11 emph lrchi adatai bcki bcko adatao lrcho 29 sqck 30 sqdt 33 sdat 32 26 sbck s0s1 efm phase detector 23bit shift register subcode sync detector subcode output subcode-q register digital pll frame sync detector protector insertor efm demodulator address generator clv servo x-tal timing generator track counter cpu interface mode selector digital output 16k sram ecc interpolator digital filter & de-emph d/a converter 8 bit data bus
digital signal processor for cdp s5l986f01 3 pin configuration S5L9286F01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 avdd1 dpdo dpfin dpfout cntvol avss1 datx xin xout wdcho lrcho adatao dvss1 bcko c2po vrefl2 vrefl1 avdd2 rchout lchout avss2 vrefh1 vrefh2 emph lkfs s0s1 reset /esp sqck sqdt sqok sbck sdat dvdd1 mute mlt mdat mck rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 flag1 flag2 flag3 flag4 flag5 /pbck dvss2 fsdw ulkfs /jit c4m c16m /we /cs xtalsel fok cdrom sram test1 efmi adatai /istat trcnt lock pbfr smef smon dvdd2 smdp smds bcki testv dspeed lrchi
S5L9286F01 digital signal processor for cdp 4 pin description pin no symbol io description 1 avdd1 - analog vcc1 2 dpdo o charge pump output for digital pll 3 dpfin i filter input for digital pll 4 dpfout o filter output for digital pll 5 cntvol i vco control voltage for digital pll 6 avss1 - analog ground1 7 datx o digital audio output data 8 xin i x'tal oscillator input 9 xout o x'tal oscillator output 10 wdcho o word clock output of 48bit/slot (88.2khz) 11 lrcho o channel clock output of 48 bit/slot (44.1khz) 12 adatao o serial audio data output of 48 bit/slot (msb first) 13 dvss1 - digital ground1 14 bcko o audio data bit clock output of 48 bit/slot (2.1168mhz) 15 c2po o c2 pointer for output audio data 16 vrefl2 i input terminal2 of reference voltage "l" (floating) 17 vrefl1 i input terminal1 of reference voltage "l" (gnd connection) 18 avdd2 - analog vcc2 19 rchout o right-channel audio output through d/a converter 20 lchout o left-channel audio output through d/a converter 21 avss2 - analog ground2 22 vrefh1 i input terminal1 of reference voltage "h" (vdd connection) 23 vrefh2 i input terminal2 of reference voltage "h" (floating) 24 emph o h: emphasis on, l: emphasis off 25 lkfs o the lock status output of frame sync 26 s0s1 o output of subcode sync signal(s0+s1) 27 reset i system reset at "l" 28 /esp i esp function on/off control ("l": esp function on, "h": esp function off) 29 sqck i clock for output subcode-q data
digital signal processor for cdp s5l986f01 5 pin description (continued) pin no symbol io description 30 sqdt o serial output of subcode-q data 31 sqok o the crc (cycle redundancy check) check result signal output of subcode-q 32 sbck i clock for output subcode data 33 sdat o subcode serial data output 34 dvdd1 - digital vdd1 35 mute i mute control input ("h": mute on) 36 mlt i latch signal input from micom (schmit trigger) 37 mdat i serial data input from micom (schmit trigger) 38 mck i serial clock input from micom (schmit trigger) 39 rd7 i/o sram data i/o port 8 (msb) 40 rd6 i/o sram data i/o port 7 41 rd5 i/o sram data i/o port 6 42 rd4 i/o sram data i/o port 5 43 rd3 i/o sram data i/o port 4 44 rd2 i/o sram data i/o port 3 45 rd1 i/o sram data i/o port 2 46 rd0 i/o sram data i/o port 1 (lsb) 47 flag1 i/o monitoring output for error correction (ra0) 48 flag2 i/o monitoring output for error correction (ra1) 49 flag3 i/o monitoring output for error correction (ra2) 50 flag4 i/o monitoring output for error correction (ra3) 51 flag5 i/o monitoring output for error correction (ra4) 52 /pbck i/o output of vco/2 (4.3218mhz) (ra5) 53 dvss2 i/o digital ground 2 54 fsdw i/o window or unprotected frame sync (ra6) 55 ulkfs i/o frame sync protection state (ra7) 56 /jit i/o display of either ram overflow or underflow for + 4 frame jitter margin (ra8) 57 c4m i/o only monitoring signal (4.2336mhz) (ra9) 58 c16m i/o 16.9344mhz signal output(ra10) 59 /we i/o terminal for test 60 /cs i/o terminal for test
S5L9286F01 digital signal processor for cdp 6 pin description (continued) pin no symbol io description 61 xtalsel i mode selection1 (h: 33.8688mhz, l: 16.9344mhz) 62 fok i the input for fok signal of servo 63 cdrom i mode selection2 (h: cd-rom, l: cdp) 64 sram i test input terminal (gnd connection) 65 test1 i test input terminal (gnd connection) 66 efmi i efm signal input 67 adatai i serial audio data input of 48 bit/slot (msb first) 68 /istat o the internal status output 69 trcnt i tracking counter input signal 70 lock o output signal of lkfs condition sampled pbfr/16 (if lkfs is "h", lock is "h", if lkfs is sampled "l" at least 8 times by pbfr/16, lock is "l".) 71 pbfr o write frame clock (lock: 7.35khz) 72 smef o lpf time constant control of the spindle servo error signal 73 smon o on/off control signal for spindle servo 74 dvdd2 - digital vdd2 75 smdp o spindle motor drive (rough control in the speed mode, phase control in the phase mode) 76 smds o spindle motor drive (velocity control in the phase mode) 77 bcki i audio data bit clock input of 48 bit/slot (2.1168mhz) 78 testv i test input terminal (gnd connection) 79 dspeed i test input terminal (vdd connection) 80 lrchi i channel clock input of 48 bit/slot (44.1khz)
digital signal processor for cdp s5l986f01 7 absolute maximum ratings electrical characteristic dc characteristic (vcc = 5v, vss = 0v, ta=25 o c , unless otherwise specified) notes: related pins 1 xtalsel, test0, cdrom, sram, test1, efmi, adatai, bcki, dspeed & lrchi 2. all bi-directional pins, reset, mlt, mck, mdat, mute, trcnt 3. all output pins except /istat, oscilator, dpfout 4. /istat 5. smef, smdp, smsd, dpdo characteristic symbol value unit supply voltage v dd -0.3 ? 7.0 v input voltage v i -0.3 ? 7.0 v output voltage v o -0.3 ? 7.0 v operating temperature t opr -20 ? 75 o c storage temperature t stg -40 ? 125 o c item symbol test condition min typ max unit high input voltage1 v ih1 (note1) 0.7v dd ?? v low input voltage1 v il1 ?? 0.3v dd v high input voltage2 v ih2 (note2) 0.8v dd ?? v low input voltage2 v il2 - ? 0.2v dd v high output voltage1 v oh1 i oh = ? 1ma, (note3) v dd ? 0.5 ? v dd v low output voltage1 v ol1 i ol = 1ma, (note3) 0 ? 0.4 v high output voltage2 v oh2 i oh = ? 1ma, (note4) v dd ? 0.5 ? v dd v low output voltage2 v ol2 i ol = 2ma, (note4) 0 ? 0.4 v input leakage current i lkg v i = 0 ? v dd , (note5) ? 5 ? 5 a tri-state output leakage current i olkg v o = 0 ? v dd , (note5) ? 5 ? 5 a
S5L9286F01 digital signal processor for cdp 8 ac characteristic when pulse is input to xin, vcoi pin (vcc=5v, vss=0v, ta=25 o c , unless otherwise specified) item symbol min typ max unit high level pulse width t wh 13 ?? ns high level pulse width t wl 13 ?? ns pulse frequency t ck 26 ?? ns input high level v ih v dd ? 1.0 ?? v input low level v il ?? 0.8 v rising & falling time t r ,t f ?? 8ns vih vihx0.9 vil*0.1 vil vdd/2 twh twl tck tr tf
digital signal processor for cdp s5l986f01 9 mck, mdat, mlt & trcnt (vcc=5v, vss=0v, ta=25 o c , unless otherwise specified) characteristic symbol min typ max unit clock frequency f ck1 --1mhz clock pule width t w 300 - - ns setup time t su 300 - - ns hold time t h 300 - - ns delay time t d 300 - - ns latch pulse width t wck1 300 - - ns trcnt, sqck frequency f ck2 --1mhz trcnt, sqck pulse width t wck2 300 - - ns mck mdat mlt trcnt sqck sqdat 1/fck1 twck1 twck1 td tw twck2 twck2 1/fck2 th tsu th tsu
S5L9286F01 digital signal processor for cdp 10 function description micom interface the data inputted from micom is inputted to mdat and transfered by mck, and the inputted signal is loaded to control register by means of mlt. the timing chart is as follows. figure 1. micom data input timing chart table 1. control register & data note: ?;reserved control regster comment address d7~d4 data /istat pin d3 d2 d1 d0 cntl-z data control 9x zcmt - nclv crcq s0s1 cntl-s frame sync protection attenuation control ax fsem fsel wsel attm lkfs cntl-l tracking counter lower 4 bits bx trc3 trc2 trc1 trc0 /complete cntl-u tracking counter upper 4 bits cx trc7 trc6 trc5 trc4 /count cntl-w clv control dx - wb wp gain fok cntl-c clv-mode ex cm3 cm2 cm1 cm0 /(pw > 64) cntl-d double-speed fx 0 0 ds1 ds2 trcnt control regster comment address d15-d8 data /istat pin d7 d6 d5 d4 d3 d2 d1 d0 cntl-f function control 88xx - - deem era_ off -- - - hi-z cntl-h esp,monitor pin control 8dxx - - - - - - esp_ on dumb hi-z mdat mck mlt register (9x ~ fx) valid d0 d1 d2 d3 d4 d5 d6 d7 register (88xx, 8dxx) mdat mck mlt valid d0 d1 d2 d3 d4 d15 d11 d12 d13 d14 ? ?
digital signal processor for cdp s5l986f01 11 control register description ? cntl-z this register carries out the following functions: audios zero cross mute, phase pin control, phase servos control signal management, and the decision whether or not to include sqok data in sqdt. zcmt zero cross mute nclv phase servos control crcq decide whether or not to include sqok data in sqdt bit 3210 identifier zcmt - nclv crcq 0 zero cross mute is off 1 zero cross mute is on 0 phase servo operated by frame sync 1 phase servo controlled by base counter 0 sqdt output not including sqok 1 sqdt = sqok, when sos1 is ?h?.
S5L9286F01 digital signal processor for cdp 12 ? cntl-s this register sets the frame sync protection and attenuation. fwsel of cntl-d is added to define window size. . fsem, fsel frame sync protection wsel frame sync protection window size attm, mute control the frame sync attenuation ? cntl-l, u when the number of tracks to be counted is input from micom, the cntl-l, or cntl-u register loads the data into the tracking counter. this tracking counter is used for improving track jump characteristics. bit 3210 identifier fsem fsel wsel attm 002 014 108 1113 0 3t 1 7t 0 0 0 db 01- db 1 0 -12 db 1 1 -12 db
digital signal processor for cdp s5l986f01 13 ? cntl-w this register sets the clv-servos control period and gain.. wb bottom hold period control in speed mode wp peak hold period control in speed mode gain smds gain control in speed mode ? cntl-c this register sets the clv-servos operating mode. bit 3210 identifier - wb wp gain 0 xtft/32 1 xtfr/16 0 xtfr/4 1 xtfr/2 0 - 12 db 1 0 db d3 ? d0 mode smdp smsd smef smon 1000 forward h hi-z l h 1010 reverse l hi-z l h 1110 speed speed-mode hi-z l h 1100 hspeed hspeed-mode hi-z l h 1111 phase phase-mode phase-mode hi-z h 0110 xphsp speed or phase-mode hi-z or phase-mode l, hi-z h 0101 vphsp speed or phase-mode hi-z or phase-mode l, hi-z h 0000 stop l hi-z l l
S5L9286F01 digital signal processor for cdp 14 ? cntl-d this register sets the normal speed and double speed mode. .3 - .0 speed control ? cntl-e this register controls the de-emphasis. . .3 - .0 clv-servo mode control. refer to wb of cntl-w register. note: d1 bit becomes to ?l? when reset. micom must give the commands of attenuation and mute, when forward / backward searching. if not, the wrong operation ocurrs easilly during the execution when fast searching. bit 3210 identifier .3 .2 .1 .0 0 0 0 0 normal speed 0 0 1 1 double speed (2x) bit 3210 identifier .3 .2 .1 .0 1 internal digital de-emphasis 0 external analog de-emphasis
digital signal processor for cdp s5l986f01 15 tracking counter block when the number of tracks to be jumped is input from micom, the track number is loaded from mlts positive edge to the register. if cntl-l is selected, /complete signal is output to the /istat pin, and if cntl-u is selected, / count signal is output. the timing diagrams of the tracking counters are figure-3 and figure-4. figure 2. tracking counter timing diagram figure 3. /istat output signal according to the cntl register mlt cntl-l, cntl-u trcnt /istat =(/count) /istat =(/complete) n n nnnn cntl-l cntl-u cntl-c other mode mdat mlt cntl state /complete /count /(pw > 64) hi-z /istat
S5L9286F01 digital signal processor for cdp 16 efm demodulation the efm block is composed of the following parts: efm demodulator to demodulate the efm signal read from the disc, efm phase detector, and the control signal generator. efm demodulator the modulated 14 channel bit data is demodulated into 8-bit data. there are two types of demodulated data: subcode data and audio data. subcode data is input into the subcode handling block, and the audio data is stored in the internal 16 k sram, and its errors are corrected. efm phase detector the efm signal input from the disc includes 2.1609 mhz components. to detect the phase of this signal, a bit clock (/pbck) of 4.3218 mhz is used. pbck detects the phase of the efm signals edge, and sends the results to the apd0 pin. figure 4. efm phase detector timing diagram (1) when theefm signal is slower than the vco signal (2) when the efm signal is locked to the vco signal (3) when the efm signal is faster than the vco signal. vcoi pbck efmi efmd a pdo 1 2 3
digital signal processor for cdp s5l986f01 17 frame sync detect/protect/insert ? frame sync detect data is composed of units of frame, and a frame is composed of frame sync, subcode data, audio data, and redundancy data. this ic detects frame sync to maintain synchronization. ? frame sync protect/insert there are some cases in which frame sync is not detected, or detected it from other data which does not include frame sync, due to disc error or jitter. in these cases, the frame sync must be protected and inserted. to protect frame sync, a window is made by wsel of the cntl-s register. the frame sync entering this window is considered valid data, and the frame sync which leaves this window is ignored. if frame sync is not detected within the frame sync protect window, insert instead the frame sync made in the internal counter. if frame sync is inserted continuously, reaching the number of frames set by fsem and fsel of the cntl-s register, the following occurs: ulkfs becomes high, the frame sync protect window is ignored, and the frame sync detected next is accepted unconditionally. when a frame sync is accepted, the ulkfs signal becomes l, and accepts the frame sync detected within the window (refer to below table). lkfs ulkfs comment 1 0 play back frame sync and the generated sync coincide. 00 1) the play back frame sync and the generated frame sync do not coincide, but pbfr sync is detected from within the window selected by wel. 2) pbfr sync and xtfr sync do not coincide, and are not detected from within the window selected by wsel. sync insert is carried out. 01 1) immediately after the following situation: frame sync is not detected within the window, so frame is inserted in the amount set by cntl-s registers fsem and fsel. 2) if pbfr sync is still undetected after 1).
S5L9286F01 digital signal processor for cdp 18 subcode block the subcode sync signals s0 and s1 are detected in the subcode sync block. s1 is detected one frame after s0 is detected. at this time, s0+s1 signal is output to the s0s1 pin, and when the s0s1 signal is high, the s0s1 signal is output to the sdat pin. out of the data input into the efmi pin, the 14-bit subcode data is efm demodulated to 8- bit (p, q, r, s, t, u, v, w) subcode data, synchronized with the wbck signal, and output to sdat by the sbck clock. out of the 8 subcode data, only q data is stored in the 80 shift registers by the wbck signal. if the crc result is error, low is output to the sqck pin, and if not, high is output. if the cntl-z registers crcq is high, the crc result is output to the sqdt pin from when the s0 and s1 are high to sqcks negative edge. the subcode blocks timing diagram is as follows: timing relation of sqck, sqdt and s0s1 when sqen = h if subcode-q datas crcq is high, the sqok signal is output to sqdt according to the sqck, and if crcq is low, the sqok signal is not output to sqdt. figure 5. subcode-q timing diagram timing relation of sdat and sbck sqck sqdt (crck=1) s0s1 sqok sqdt (crck=0) sqok(n) q4 q3 q2 q1 q8 q7 q80 q79 q78 q77 sqck(n+1) q4 q3 q6 q5 0 q4 q3 q2 q1 q8 q7 q80 q79 q78 q77 0 q4 q3 q6 q5 b q r s t u v w c 12345678 a wbck sbck sdat a) after pbfr goes negative edge, sbck is set to l for about 10 s. b) if s0s1 is l, subcode p is output, and if s0s1 is high, s0s1 is output. c) if there are more than 7 pulses input into the sbck pin, the subcode data p, q, r, s, t, u, v, and w data are output repeatedly.
digital signal processor for cdp s5l986f01 19 error correcting code (ecc) when disc data is damaged, it is corrected using the ecc (error correcting code) block. it uses the circ (cross interleaved reed-solomon code), correcting up to 2 errors when c1 (32, 28), and up to 4 erasures when c2 (28, 24). error correction handles the data in units of 8-bit 1 symbol. the ecc block has pointer handling function, and can generate a c1 pointer in c1 correction, and a c2 pointer in the c2 correction. the c1 and c2 pointers output a flag about the ecc-handled data to mark it as error data. this flag information signal is input into the interpolator, and used for handling the error data. also, the error correcting results can be monitored using the flag1, flag2, flag3, flag4, flag5 pins mode flag5 flag4 flag3 flag2 flag1 remark c1 no error 0 0 0 0 0 c1 correction start c1 1 error 00001 - c1 2 error 00010 - c1 irretrirvable error 0 1 1 1 1 c1 pointer set c2 no error 1 0 0 0 0 c2 correction start c2 1 error 10001 - c2 2 error 10010 - c2 3 error 10011 - c2 4 error 10100 - c2 irretrievable error 1 1 1 1 1 0 c1 pointer copy c2 irretrievable error 2 1 1 1 1 1 c2 pointer set
S5L9286F01 digital signal processor for cdp 20 interpolator / mute interpolator if a burst error occurs on the disc, sometimes data cannot be corrected even if you carry out the ecc process. the interpolator block uses the eccs c2 pointer to interpolate the data. the audio data is input into the data bus in the following order: for each l/r-ch: 8-bit c2 point, lower data 8 bits, and upper data 8 bits. if c2po pin is high, and one error has occurred, the average value interpolation is carried out, and if three consecutive errors occurred, the previous value hold interpolation is carried out. for one period of lrch, if lrch is low, r-ch data is output, and if lrch is high, l-ch data is output. please refer to figure-9 for the interpolator blocks timing diagram. figure 6. interpolation method c2 pointer a b c def g h i j b = (a+c)/2: average value interpolation f = e = d: previous value hold interpolation g = (f+h)/2: average value interpolation
digital signal processor for cdp s5l986f01 21 mute/attenuation the audio data can be muted or weakened by the attm signal of the mute pin and cntl-s register. ? zero cross mute the audio data is muted when the cntl-z registers zcmt is high, mute is high, and the upper 6 bits of audio data are all high. ?muting the audio data is in muting is the cntl-z registers zcmt is l and the mute pin is high. ? attenuation audio signal is weakened by the cntl-z registers attm and mute signal. attm mute degree of attenuation 0 0 0 db 01 ? db 10 ? 12 db 11 ? 12 db
S5L9286F01 digital signal processor for cdp 22 clv servo cntl-c, e, g1, g2, and g3 registers are selected to control the clv (constant linear velocity) servo using the data input from micom. also, the design is such that the servo control is stable when setting the speed. when setting the speed, the /(pw 64) signal can be detected from the /istat pin only if the cntl-d register is first set before the cntl-c register is selected. forward this mode rotates the spindle motor in the forward direction. the related output pin status are as follows: . reverse this mode rotates the spindle motor in the reverse direction. the related output pin status are as follows:. speed-mode the spindle motor is controlled roughly by speed mode when track jumping or efm phase is unlocked. if a period of vco is "t", the pulse width of frame sync is 22t. in case that the signal detected from efm signal exceeds 22t by noise on the disc and etc., it must be removed, if not, the right frame sync can't be detected. in this case, the pulse width of efm signal is detected by peak hold clock and bottom hold clock. ( peak hold clock is xtfr/2 or xtfr/4, and bottom hold clock is xtfr/16 or xtfr/32.) the detected value is used for synchronized frame signal. if the frame signal is less than 21t, the smdp terminal outputs "l", eaqul to 22t, outputs "hi-z", and more than 23t, ouputs "h". if the gain signal of cntl-w register is "l", the output of smdp terminal is reduced up to ? 12db, if it is "h", there is no reduction. output condition: smsd="hi-z", smef="l", smon="h". hspeed-mode the rough servo mode, which moves 20,000 tracks in high speed acts between the inside and outside of the cd. the mirror domain of track which hasn't pit is duplicated with 20khz signal to efm. in this case, servo action is unstable because the peak value of mirror signal which is longer than orignal frame sync signal which is detected. in hspeed mode, by using the 8.4672/256mhz signal against peak hold and xtfr/16 or xtfr/32 signal against bottom hold, the mirror component is removed, and hspeed servo action to be stable. he output condition is as following. smdp smsd smef smon hhi-zl h smdp smsd smef smon lhi-zl h smdp smsd smef smon ?hi-zl h
digital signal processor for cdp s5l986f01 23 phase-mode the phase mode is the mode to control the efm phase. phase difference between pbfr/4 and xtfr/4 is detected when nclv of cntl-z register is "l",and phase difference between read base counter/4 and write base counter/4 detected when nclv is "h", and the difference is outputted to smdp(fig.14). if the cycle of vco/2 signal is put as "t" and it is put as "/wp" during a "h" period of pbfr, it outputs "h" to smsd terminal from the falling edge of pbfr to the (/wp-278t) x 32, and then, outputs "l" to the falling edge of the next pbfr. (figure 7) xphsp-mode the xphsp mode is the mode used in normal operation. the lkfs signal made from frame sync block is to sampling which period is pbfr/ 16. if the sampling is "h", the phase mode is performed, and if the sampling is eight of "l" continously, speed-mode is performed automatically. the selection of peak hold period in speed-mode and selection of bottom hold period and gain in speed/ hspeed- mode is determined by cntl-w register. vphsp-mode the vphsp mode is the mode used for rough servo control. it uses vco instead of x-tal in the efm pattern test. when the range of vco center changes, vco is easily locked because the rotation of a spindle motor changes in the same direction. stop-mode this mode stops the spindle motor. smdp smsd smef smon lhi-zl l figure 7. smsd, smdp output timing diagram hi-z hi-z hi-z xtfr/4; (xtfr/8) pbfr/4; (pbfr/8) smdp 287t 288t pbfr smsd 294t 512t pbfr smsd
S5L9286F01 digital signal processor for cdp 24 figure 8. smdp output when the gain is high in speed-mode ph_pulse tb tp ph f/f (> 22t) bh f/f (> 22t) latch (22t) smdp bh_pulse efm width ph f/f (> 23t) bh f/f (> 23t) latch (23t) hi-z ( == 22t) 21t > > 23t 22t l ( <= 21t) h ( >= 23t) 1 0 11 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 j215(> 22t) j214(> 23t)
digital signal processor for cdp s5l986f01 25 digital filter the s5l9284e has a built-in fir ( finite impulse response) digital filter. this digital filter consists of 8fs over sampling filter. figure 9. digital filter block diagram 51 th fir f s 13 th fir 2f s 9 th fir 4f s 51 th fir f s * 9 th fir 2f s * 8f s 16 bits 4f s * 16 bits (a) normal speed play mode (b) doubll speed play mode
S5L9286F01 digital signal processor for cdp 26 filter characteristic ripple in passband : within + 0.5db attenuation in stopband: below -42db figure 10. filter characteristic curve frequency (fs) (b) double speed log magntude(db) frequency (fs) (a) normal speed log magntude(db)
digital signal processor for cdp s5l986f01 27 digital audio out this block serially outputs 2-channel and 16-bit data with the digital audio interface format as reference. digital audio interface format for cd figure 11. digital audio out format preamble the preamble is used to distinguish the datas block and l/r ch data . figure 12. preamble signal preamble modulated "0" 8-bit modulated 16-bit audio data v u c p control signal left channel right channel 1 lrch 191 r 0l 0r 1l 1r 190 r 191l 191r 0l -r 190 l t 192 t 0l: l-ch format including the block sync preamble 1l ? 191l: l-ch format including the l-ch sync preamble 0r ? 191r: r-ch format including the r-ch sync preamble 8.4672 mhz l-ch. sync (except block sync) r-ch. sync block sync (l-ch.)
S5L9286F01 digital signal processor for cdp 28 control signal (1) validity bit: shows the presence of error in 16-bit audio data: ?h?=error, ?l?=valid data (2) user definable bit: subcode data out figure 13. digital audio data out timing diagram (3) channel status bit: subcode-qs upper 4-bit data output, shows number of channels, pre-emphasis, copy, cdp- category, etc. figure 14. channel status data out timing diagram (4) parity bit: makes even parity figure 15. digital audio data out timing diagram 48bits/slot sync pattern p q r s t u v w sos1 pbfr sbck sbdt sos1 pbfr sqdt id0 id1 copy emph 1 5 10 15 20 25 30 35 40 45 50 10 15 14 13 12 11 8 7 6 5 4 3 2 1 9 10 15 14 13 12 11 8 7 6 5 4 3 2 1 9 l-ch (msb) 16 r-ch (msb) 16 t lrch (44.1khz) bck (2.12mh z) wdch (88.2khz) adata
digital signal processor for cdp s5l986f01 29 digital pll this device contains digital pll in order to obtain the stable channel clock for demodulating efm signal. the block diagram of digital pll is as follows. figure 16. digital pll circuit diagram phase comparator low pass filter voltage cotrolled oscillator 1/n devider digital main pll x'tal efmi frequency synthesizer /pbck
S5L9286F01 digital signal processor for cdp 30 d/a converter (digital to analog converter) the s5l9284e has a built-in 16-bit d/a converter. digital audio data is a 2's complement serial format (msb sirst), vref terminal vref, the reference voltage across a resister-ladder, is usually recommended with vrefh1=5v, vrefl1=0v. one way of avoiding an amplitude mismatching between the vref and op amp input connected to the output of d/ a converter is to reduce the analog output amplitude with vrefh2=5v and vrefl2=0v (at this time about 100 f capacitor should be connected from vreh1 and vrefl1 to gnd). by the effect of built-in rh and rl with this choice, the maximum analog output amplitude result in a narrow range of about 1.5 ~ 3.5v for 0db playback. figure 17. vref relation circuit d/a converter electrical characteristic the d/a converter electrical characteristic built in s5l9826f01 is as follows. (v dd = 5v, v ss = 0v, ta = 25 o c) characteristics symbol test conditon min typ max unit total harmonic distortion thd data=1khz, 0db ?? 0.08 % signal to noise ratio s/n v dd =4.5v data=1khz, 0db ? 92 ? db cross-talk ct data=1khz, 0db ?? 85 ? db voltage dividing d/a converter d3 - d0, d15 - d7 vrefh1 vrefh2 vrefl1 vrefl2 analog mux control circuit d6 - d4 rchout lchout
digital signal processor for cdp s5l986f01 31 digital de-emphasis the emphasis/de-emphasis circuit is used for improving s/n ration by decreasing high frequency noise in case of the frequency characteristic of signal not being changed. the digital de-emphasis circuit, which can de-emphasise the signal emphasised on disc, is built-in s5l9826f01, and the frequency characteristic is as follows. frequency characteristic of de-emphasis circuit frequency characteristic 1khz -0.51db 5khz -4.5db 10khz -7.59db 20khz -9.5db
S5L9286F01 digital signal processor for cdp 32 esp interface block introduction because the location of normal table cd player used in family is fixed, it is possible to play music stabilitable when the degree of damage on disc is in limit range. but in now, it is general that user can hear music when moving by walkman-cd player. in this case, if user has been shocked suddenly, it often happens that music playing is unstable. on this, the esp interface block is added to s5l9826f01 for realizing the function of anti-shock. the application circuit of using npc anti-shock memory controller ic sm5859af and s5l9826f01 is as follows. figure 18. esp interface application the operation of s5l9826f01 is different when normal operation and forming anti- shock function with external esp ic. from figure19, the operation of part b composed by digital filter, digital de-emphasis and 16-bit d/a converter in s5l9826f01 and part a except part b is separated. when anti-shock function is used in case of /esp pin being "l", part a block operates in double speed and part b block operates in normal speed. micor- control ymdata ymclk ymld zsense /esp part a 16k sram efm demodulation ecc sub-q demodulation clv-servo interpolation part b digital filter digital de_ emphasis d/a converter s5l9286e /jit sos1 vss lrcko bcko adatao lrcki bcki adatai sm5859 yblkck yflsg yfclk ylrck ysck ysrdata zlrck zsck zsrdata /ras /we a0 to a10 d0 to d3 ncas /ras /we a0 to a10 d0 to d3 /cas vss /oe dram
digital signal processor for cdp s5l986f01 33 that is, after efm demodulation, error correction and interpolation block operation in double speed, audio data is inputted to esp ic which is the anti-shock memory controller. audio data received by esp ic is saved in external memory and then inputted to s5l9284e. in part b of s5l9826f01, the data is dealed with in normal speed and then outputted . the anti-shock function is not used in case of /esp terminal being "h". the interface timing diagram of esp ic is as follows. figure 19. timing chart of signal output to esp ic figure 20. timing chart of signal esp ic outpu to dsp lrcho bcko a datao d15 d14d13d12d11d10d9d8 d7d6 d5 d4 d3 d2 d1d0 d15 d15 d14 d13 d12 d11 d1 d0 88.2khz d14d13d12d11d10d9d8 d7d6d5d4d3d2d1d0 lrchi bcki a datai d14d13d12d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d15 d14 d13 d12 d 11 d1 d0 44.1khz
S5L9286F01 digital signal processor for cdp 34 application information micom register the s5l9826f01 uses the exactly same micom command as s5l9282e (dsp+dac) except one address addition. adress: $88 data: d1(deem) h: when internal digital de-emphasis circuit is used. l: when external analog de-emphasis circuit is used. d1 bit is cleared 'l' by reset. during fast search, for example forward or backward, micom must order attenuation to dsp ic. if micom dosen't order attenuation to dsp, the dsp ic may cause malfunction of erasuer correction during fast search. esp part if esp ic is not used, you must connect follow pins to gnd. ? lrchi ?adatai ? bcki
digital signal processor for cdp s5l986f01 35 package dimension 80-qfp-1420c #80 20.00 + 0.20 23.90 + 0.30 14.00 + 0.20 17.90 + 0.30 #1 0.80 0.35 + 0.10 0.15 max (0.80) 0.15 + 0.10 - 0.05 0-8 0.10 max 0.80 + 0.20 0.05 min 2.65 + 0.10 3.00 max 0.80 + 0.20

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